Semiconductors are widely used for integrated circuits for electronic applications, including radios, televisions, and personal computing devices, as examples. Such integrated circuits typically use multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. To provide the necessary signal and power interconnections for the multiplicity of semiconductor devices, many integrated circuits now include multiple levels of metallization.
The semiconductor industry continuously strives to decrease the size of the semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of the circuits necessary for today's advanced semiconductor products. The increasing density has led to the need for more metallic layers, typically of aluminum and more recently of copper, to provide the circuit interconnections. With the increasing number of metallic interconnection layers, more manufacturing steps and cost are required to form the interconnections than the transistors and diodes in the semiconductor device. For high complexity, high density chips with six or more layers of metallization, the total length of the layered interconnect wiring in the chip can be of the order of a mile. The signaling speed among on-chip devices provided by these interconnections has become a significant factor in chip performance. The resistance of the interconnecting wiring generally increases as a consequence of its width-height product being reduced faster than its length is shortened, which further aggravates the signaling-speed problem.
One solution to the problem of line resistance is by using copper interconnects. While copper has the desirable property of low resistivity, it has the problem of being difficult to etch as well as having the propensity of drifting and diffusing into any surrounding interlevel dielectric exposed to the surface of the copper.
To address the issue of copper being difficult to etch, a layered and patterned metal interconnect structure is conventionally formed in the upper layers of an integrated circuit to provide the necessary circuit connections for the various semiconductor devices in the integrated circuit such as transistors and diodes. In high-density integrated circuits, damascene techniques are used to form and deposit metal lines and vias for the desired interconnections in a surrounding dielectric layer.
To address the problem of copper diffusing into the ILD, barrier materials are used to surround the copper to prevent diffusion. Barrier materials can include metallic materials such as TiN or TiW, or dielectric materials such as SiN. One common technique used to encapsulate the top surface of a copper line is to deposit a dielectric layer over the surface of the wafer after each layer of copper interconnect is deposited. This dielectric layer typically has a higher k than the low k ILD. While the dielectric makes a good, non-conductive diffusion barrier, the presence of a global dielectric layer increases the effective k of the solution and increases the capacitive coupling between metallization. What is needed is a method to utilize a low k dielectric ILD without the loss of its low-k properties including k degradation during the etch process or loss of effective k because of the use of a higher k encapsulation layer.